# New Chipset, Faster Memory.... **URL:** \ **Category:** NYSpeed Off Topic\ **Created:** [March 14, 2007, 1:34pm UTC](https://forums.speedlife.net/t/new-chipset-faster-memory/25870 "2007-03-14T13:34:13Z")\ **Posts on this page:** 18\ **Page:** 1
**Author:** ![system](https://canada1.discourse-cdn.com/flex034/uploads/speedlife/original/2X/b/b7170c8eddc0b95ece6b88172b2f416a08489a45.png) [@system](https://forums.speedlife.net/u/system)\ **Post date:** [March 14, 2007, 1:34pm UTC](https://forums.speedlife.net/t/new-chipset-faster-memory/25870/1 "2007-03-14T13:34:13Z")
Looks like intel is ahead of the game here…Hope AMD comes back with some punches…Core 2 Duo revised already… [http://www.tgdaily.com/2007/03/14/cebit2007\_intel\_bearlake/](http://www.tgdaily.com/2007/03/14/cebit2007_intel_bearlake/) ---
**Author:** ![Bacon](https://yyz2.discourse-cdn.com/flex034/user_avatar/forums.speedlife.net/bacon/32/7230_2.png) [@Bacon](https://forums.speedlife.net/u/Bacon)\ **Post date:** [March 14, 2007, 3:01pm UTC](https://forums.speedlife.net/t/new-chipset-faster-memory/25870/2 "2007-03-14T15:01:35Z")
The sleeping giant has awakened. ---
**Author:** ![ryanmcell](https://yyz2.discourse-cdn.com/flex034/user_avatar/forums.speedlife.net/ryanmcell/32/7510_2.png) [@ryanmcell](https://forums.speedlife.net/u/ryanmcell)\ **Post date:** [March 14, 2007, 3:41pm UTC](https://forums.speedlife.net/t/new-chipset-faster-memory/25870/3 "2007-03-14T15:41:37Z")
Mmmmm no price posted? Sounds awesome, despite the heavy pricetag I imagine. ---
**Author:** ![Nikuk](https://yyz2.discourse-cdn.com/flex034/user_avatar/forums.speedlife.net/nikuk/32/7254_2.png) [@Nikuk](https://forums.speedlife.net/u/Nikuk)\ **Post date:** [March 14, 2007, 3:42pm UTC](https://forums.speedlife.net/t/new-chipset-faster-memory/25870/4 "2007-03-14T15:42:19Z")
neat. more importanly, current gen prices will start dropping. mmmm ---
**Author:** ![Nikuk](https://yyz2.discourse-cdn.com/flex034/user_avatar/forums.speedlife.net/nikuk/32/7254_2.png) [@Nikuk](https://forums.speedlife.net/u/Nikuk)\ **Post date:** [March 14, 2007, 3:42pm UTC](https://forums.speedlife.net/t/new-chipset-faster-memory/25870/5 "2007-03-14T15:42:39Z")
[quote=“ryanmcell,post:3,topic:25870"”] Mmmmm no price posted? Sounds awesome, despite the heavy pricetag I imagine. [/quote] too soon junior ---
**Author:** ![Rx3](https://yyz2.discourse-cdn.com/flex034/user_avatar/forums.speedlife.net/rx3/32/7194_2.png) [@Rx3](https://forums.speedlife.net/u/Rx3)\ **Post date:** [March 14, 2007, 4:35pm UTC](https://forums.speedlife.net/t/new-chipset-faster-memory/25870/6 "2007-03-14T16:35:39Z")
CRAP! Why do they always do this after I buy a new computer? :mad: ---
**Author:** ![system](https://canada1.discourse-cdn.com/flex034/uploads/speedlife/original/2X/b/b7170c8eddc0b95ece6b88172b2f416a08489a45.png) [@system](https://forums.speedlife.net/u/system)\ **Post date:** [March 15, 2007, 6:14am UTC](https://forums.speedlife.net/t/new-chipset-faster-memory/25870/7 "2007-03-15T06:14:32Z")
I’m just waiting for quad-core and DDR3 memory…I am a AMD guy but will buy product dependent on benchmarks and whoever is better. ---
**Author:** ![Fry](https://yyz2.discourse-cdn.com/flex034/user_avatar/forums.speedlife.net/fry/32/7284_2.png) [@Fry](https://forums.speedlife.net/u/Fry)\ **Post date:** [March 15, 2007, 8:17am UTC](https://forums.speedlife.net/t/new-chipset-faster-memory/25870/8 "2007-03-15T08:17:18Z")
Haha I’m still rocking out an Athlon XP. :mamoru: I’m too cheap to buy a matching pair of ram sticks so I’m not even in dual channel. 😛 ---
**Author:** ![boardjnky4](https://avatars.discourse-cdn.com/v4/letter/b/96bed5/32.png) [@boardjnky4](https://forums.speedlife.net/u/boardjnky4)\ **Post date:** [March 29, 2007, 6:27am UTC](https://forums.speedlife.net/t/new-chipset-faster-memory/25870/9 "2007-03-29T06:27:34Z")
your link is now dead, but check this out: > **[Intel spills beans on Core 2 successor: SSE4, faster virtualization, bigger...](https://arstechnica.com/gadgets/2007/03/intel-spills-beans-on-core-2-successor-sse4-faster-virtualization-bigger-caches/)** > > The 45nm successor to the popular Core 2 line is on its way, and it's bringing … Intel spills beans on Core 2 successor: SSE4, faster virtualization, bigger caches By Jon Stokes | Published: March 28, 2007 - 02:23PM CT At a press conference today, Intel’s Pat Gelsinger revealed fresh details of the company’s forthcoming 45nm processor family, codenamed Penryn. Penryn is the 45nm successor to the Merom/Conroe/Woodcrest microarchitecture that underlies the popular 65nm Core 2 Duo processor line. Related Stories ``` * Intel's vPro brand arrives * Can AMD keep up with demand? * Taking the temperature of the MacBook Pro * Quad-core Kentsfield reviews hit the 'Net ``` Gelsinger opened the briefing with a discussion of the success of the company’s “tick-tock” model of processor innovation, a model in which process shrinks and major architectural revisions are rolled out on a staggered two-year time scale. “Today’s disclosures clearly lay out that this engine is delivering and delivering on track,” said Gelsinger, responding to what he characterized as initial skepticism that the model could work. Gelsinger then moved on to discuss Penryn, which is the first product that will be produced on Intel’s new high-k dielectric 45nm process. Penryn is more than just a shrink—it’s a derivative of Core 2 Duo (codenamed Merom) with a number of improvements. Gelsinger laid out those improvements in more detail than we’ve seen so far, so I’ll outline them below. Penryn’s improvements: SSE4 support, better virtualization Penryn’s back end boasts two major advances over its predecessor. First is a new radix-16 divider that offers a 2x performance improvement on division operations vs. Core 2 Duo. The fast divider also speeds up a range of operations that depend on the divider hardware, like the square root function. Penryn’s SQRT operation is 4x the speed of Core 2. The other major back-end improvement is support for the SSE4 extensions, a group of 50 new vector instructions aimed at speeding up media and other data-parallel applications. SSE4 will be paired with a new “Super Shuffle Engine,” a full-width, single-pass, 128-bit shuffle unit. This will enable Penryn’s vector hardware to perform 128-bit shuffle operations (e.g. pack, unpack, packed shift) in a single clock cycle. The beefed up shuffle capabilities will help Penryn align incoming vector data in the SSE registers so that the execution hardware can go to work on it. Intel claims that SSE4, in combination with other new features that I’ll describe shortly, will offer Penryn a performance improvement of as much as 40 percent over Core 2 Duo on some software like video codecs, and as much as 20 percent on games. A big part of this performance boost will no doubt be due to the higher frontside bus speeds that Penryn will support. Penryn-based Xeon systems will sport frontside bus speeds of up to 1600MHz. Intel estimates that the increased FSB speed could yield up to a 45 percent speedup on bandwidth- and floating-point-intensive applications on the fastest Penryn-based quad-core systems. To go with the faster FSB, Intel has also upped the cache on the Penryn processors. Dual-core parts will have 6MB of shared L2, while quad-core products will have 12MB. These caches will also be paired with an enhanced version of Intel’s Smart Cache technology. The new Smart Cache will let Penryn speculatively execute across cache lines, eliminating the typical stall associated with non-aligned loads. Intel will take advantage of the 45nm process not only to increase the amount of cache, but also to raise clockspeeds without significantly boosting power dissipation. Penryn parts will eventually reach the 3GHz mark, and may go even higher. The TDP numbers for Penryn desktop quad-core parts will be 95 and 130 watts, with desktop dual-core parts coming in at a 65W TDP. The TDP numbers for the 45nm Xeon will be 50W/80W/120W, depending on clockspeed. For dual-core, the numbers are 40W/65W/80W. For Penryn-based mobile parts, Intel will introduce a new low-power state that they’re calling Deep Power Down. In the new state, the core clock is turned completely off, along with the L1 and L2 caches. Process state is saved in a special part of the processor so that the system can be restored on wakeup. The other big power-related news about Penryn is that it will an enhanced version of Intel’s Dynamic Acceleration Technology. The new version will let Penryn detect when one core is largely idle—and thus not drawing much power—so that it can boost the clockspeed of the other, more active core while remaining in the same power envelope. For single-threaded applications where only one core is used, this will enable Penryn to speed up that one thread by devoting more power to the core on which it’s running. Penryn boosts virtualization One of the major features that Penryn brings to the table is a pretty important improvement to the performance of its Virtualization Technology (VT). Specifically, the performance of its virtual machine (VM) exit and VM entry instructions has been boosted so that VM transition times decrease by an average of 25 to 75 percent. Right now, a lot of folks who’re testing out VT have been disappointed that its performance isn’t much better than existing, non-VT-based virtualization solutions like VMware. Specifically, VMware products use a binary translation engine that ingests regular x86 OS code and produces a “safe” subset; VMware claims that this binary translation approach is as fast as, or faster, than VT-based approaches because the OS doesn’t have to do costly VM transitions in order to execute privileged instructions. (These claims are debated; I’m merely reporting the fact that they are made.) A major decrease in VM transition times will help the performance of VT-based solutions like Xen, and it would make the “which virtualization package to use?” debate even more about managment and less about relative performance than it already is. All told, Intel will introduce six Penryn products this year, spanning the full range of segments from ultra-mobile to server. A full fifteen Penryn products are currently in development. ---
**Author:** ![system](https://canada1.discourse-cdn.com/flex034/uploads/speedlife/original/2X/b/b7170c8eddc0b95ece6b88172b2f416a08489a45.png) [@system](https://forums.speedlife.net/u/system)\ **Post date:** [March 29, 2007, 6:30am UTC](https://forums.speedlife.net/t/new-chipset-faster-memory/25870/10 "2007-03-29T06:30:49Z")
cool read! ---
**Author:** ![FightinMike](https://avatars.discourse-cdn.com/v4/letter/f/7bcc69/32.png) [@FightinMike](https://forums.speedlife.net/u/FightinMike)\ **Post date:** [March 29, 2007, 8:06am UTC](https://forums.speedlife.net/t/new-chipset-faster-memory/25870/11 "2007-03-29T08:06:15Z")
Supposedly AMD is working on “true” dual core. Where Intel has merely tied two cores together on die, AMD is looking at making 2 integrated processors tied together at the base level. Nothings materialized yet, but the 45nm from Intel are still this same priciple. ---
**Author:** ![itsJim](https://avatars.discourse-cdn.com/v4/letter/i/c67d28/32.png) [@itsJim](https://forums.speedlife.net/u/itsJim)\ **Post date:** [March 29, 2007, 9:37am UTC](https://forums.speedlife.net/t/new-chipset-faster-memory/25870/12 "2007-03-29T09:37:23Z")
I thought that AMD had true dual core from the beginning and that Intel only recently got true dual core in the core 2 duo ---
**Author:** ![FightinMike](https://avatars.discourse-cdn.com/v4/letter/f/7bcc69/32.png) [@FightinMike](https://forums.speedlife.net/u/FightinMike)\ **Post date:** [March 29, 2007, 12:38pm UTC](https://forums.speedlife.net/t/new-chipset-faster-memory/25870/13 "2007-03-29T12:38:12Z")
Core 2 duos are still independent processors tied in with a cache. ---
**Author:** ![\_Karu](https://yyz2.discourse-cdn.com/flex034/user_avatar/forums.speedlife.net/_karu/32/7602_2.png) [@\_Karu](https://forums.speedlife.net/u/_Karu)\ **Post date:** [March 29, 2007, 12:42pm UTC](https://forums.speedlife.net/t/new-chipset-faster-memory/25870/14 "2007-03-29T12:42:42Z")
law of diminishing return will soon end the idea of 2…4…8 processors… performance gain won’t be that great anymore… another good question though: when will moore’s law going to slow and possibly end? i mean…this processor will become absolute junk in couple years anyway… ---
**Author:** ![Bacon](https://yyz2.discourse-cdn.com/flex034/user_avatar/forums.speedlife.net/bacon/32/7230_2.png) [@Bacon](https://forums.speedlife.net/u/Bacon)\ **Post date:** [March 29, 2007, 6:39pm UTC](https://forums.speedlife.net/t/new-chipset-faster-memory/25870/15 "2007-03-29T18:39:06Z")
It won’t necessarily end, it will just evolve into new ideas and goals until there is no more profit to be found. ---
**Author:** ![FightinMike](https://avatars.discourse-cdn.com/v4/letter/f/7bcc69/32.png) [@FightinMike](https://forums.speedlife.net/u/FightinMike)\ **Post date:** [March 29, 2007, 10:34pm UTC](https://forums.speedlife.net/t/new-chipset-faster-memory/25870/16 "2007-03-29T22:34:48Z")
I dunno, quantum computing seems like a pipe dream. Another example of sound theory, impractical IRL. More than likely the current implementation of transistor switching will be too slow. IMO we need to work on bringing machine language up a few degrees in sophistication. Bit flipping is very limited to physical hardware, more flipping means more hardware. Thats why die shrinking is so important to bit operations per second, its all about how many transistors you can squeeze on a certain amount of area. Currently the research side is lacking, the big companies are too concerned with making money off of the current developement and will run themselves into the ground like certain car companies _cough_blueoval_cough_. ---
**Author:** ![ILCisDEAD](https://avatars.discourse-cdn.com/v4/letter/i/a87d85/32.png) [@ILCisDEAD](https://forums.speedlife.net/u/ILCisDEAD)\ **Post date:** [March 29, 2007, 10:39pm UTC](https://forums.speedlife.net/t/new-chipset-faster-memory/25870/17 "2007-03-29T22:39:31Z")
oh believe me thats not the reason why ford is running straight into a wall… and I can only imagine in \< 5 years having a core per process… or maybe 2 or 5 dedicated to a process… ugh… well when they fuck around with their 12mb caches… i’ll have fun with my 512. or 1mb cache i’m soo pissed i don’t even remember what i have ☹ ---
**Author:** ![boardjnky4](https://avatars.discourse-cdn.com/v4/letter/b/96bed5/32.png) [@boardjnky4](https://forums.speedlife.net/u/boardjnky4)\ **Post date:** [March 30, 2007, 6:13am UTC](https://forums.speedlife.net/t/new-chipset-faster-memory/25870/18 "2007-03-30T06:13:06Z")
Intel and AMD are suffering more from their implementation then anything. They are building sooooo much backwards compatability into their chips that it is not allowing them to move forward anymore. What it comes down to is that the intel/amd instruction set is huge. they support a shit ton of assembly instructions, half of which are more or less useless and should be done away with. The Golden Handcuffs